module sort(
input clk,
input rst_p,
input [7:0]data1,
input [7:0]data2,
input [7:0]data3,
input data_valid,
output reg[7:0]max,
output reg[7:0]mid,
output reg[7:0]min,
output reg data_valid_o
);
always@(posedge clk or negedge rst_p)begin
if(rst_p)begin
max <= 8'b0;
mid <= 8'd0;
min <= 8'b0;
end
else if((data1>=data2)&&(data1>=data3))begin
if(data2>=data3)begin
max <= data1;
mid <= data2;
min <= data3;
end
else begin
max <= data1;
mid <= data3;
min <= data2;
end
end
else if((data2>data1)&&(data2>=data3))begin
if(data3>=data1)begin
max <= data2;
mid <= data3;
min <= data1;
end
else begin
max <= data2;
mid <= data1;
min <= data3;
end
end
else if((data3>data1)&&(data3>data2))begin
if(data1>=data2)begin
max <= data3;
mid <= data1;
min <= data2;
end
else begin
max <= data3;
mid <= data2;
min <= data1;
end
end
end

always@(posedge clk)
data_valid_o <= data_valid;


endmodule
